In semiconductor memory devices and other semiconductor integrated circuits, the devices are typically placed in a test mode of operation during manufacture to ensure that the devices operate as required. A variety of different techniques are utilized to place the device in the a particular mode of operation, such as a test mode of operation. For example, in a dynamic random access memory (“DRAM”), a particular sequence of applied control signals may be applied to place the device in the test mode of operation, such as activating a column address strobe signal CAS before a row address signal RAS, which does not occur during normal operation of the memory device. Another conventional method for placing a memory device in a test mode of operation is to apply a “supervoltage” to a particular pin of the memory device. The supervoltage has a value greater than the normal operating range of signals applied on the pin, and when circuitry within the memory device senses the supervoltage, the device begins operating in the test mode.
In some situations, however, a particular technology limits the utilization of the supervoltage approach to placing the memory device in the test mode. For example, in a static random access memory (“SRAM”), at least some external pins of the memory typically include diodes coupled between the pin and a supply voltage to provide clamping of signals applied to the pin. FIG. 1 is a functional diagram illustrating an external pin 100 of an SRAM coupled to internal circuitry 102 in the SRAM. A clamping diode 104 is coupled between the external pin and a supply voltage VCC to limit or “clamp” voltages on the external pin 100 and thereby prevent such voltages from damaging the internal circuitry 102. When such diodes 104 are utilized, it is not possible to apply a supervoltage to the external pin 100 to place the SRAM in a test mode of operation since the clamping diode 104 limits the voltage on the external pin to a threshold voltage VT of the diode above the supply voltage VCC. This is true because the clamping diode 104 prevents the voltage on the pin from being driven to a level sufficiently above normal operating levels to allow the internal circuitry 102 to reliably detect the presence of the supervoltage and place the SRAM in the test mode of operation. Moreover, a permissible range of values for the supply voltage VCC may include the value VCC+VT and thus this voltage cannot not be used to place the SRAM in the test mode.
With any technique for placing an integrated circuit in a test mode of operation, it must be extremely unlikely that the test mode can be inadvertently entered by a user of the memory device. It must be extremely unlikely that the test mode will be inadvertently entered because entering the test mode will typically render the device inoperable. For example, in a typical memory device, during the test mode redundant circuits are utilized to replace defective elements in the device. If the test mode of the device is reentered, such redundant elements are typically disabled to allow for testing of the device. Thus, if a customer were to inadvertently enter the test mode, the device would become inoperable since the redundant elements being utilized to replace defective elements in the memory device will be disabled.
There is a need for a reliable technique to place a wide variety of integrated circuits into a test or other desired mode of operation where the use of one or more of the existing approaches is not viable.